Semiconductor memory and refresh cycle control method
US7583553B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 8, 2007 |
| Grant date | Sep 1, 2009 |
| Priority date | — |
| Expiry date | Jul 11, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory and a refresh cycle control method that reduce a standby current by properly changing a refresh cycle according to the temperature of the semiconductor memory. A temperature detection section detects the temperature of the semiconductor memory. A cycle change control section sends a cycle change signal for changing a refresh cycle when the temperature of the semiconductor memory reaches a predetermined cycle change temperature. A refresh timing signal generation section generates a refresh timing signal and changes the cycle of the refresh timing signal in response to the cycle change signal. A constant current generation circuit generates an electric current for generating the refresh timing signal. A low-temperature constant current setting circuit designates the level of the electric current generated in the case that the temperature of the semiconductor memory is lower than or equal to the cycle change temperature. A high-temperature constant current setting circuit designates the level of the electric current generated in the case that the temperature of the semiconductor memory is higher than the cycle change temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.