Wireless communication system and method using clock swapping during image rejection calibration
US7583946B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2006 |
| Grant date | Sep 1, 2009 |
| Priority date | — |
| Expiry date | Apr 17, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B17/21
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A wireless communication receiver is disclosed that operates in a test mode to determine image correction information that is used to suppress undesired image signals when the receiver switches to a normal operational mode. In one embodiment, the receiver includes a frequency synthesizer coupled by a quadrature divider to an in-phase (I) mixer and a quadrature mixer. The mixers are coupled by respective analog to digital converters (ADCs) to respective I and Q channel inputs of a digital signal processor (DSP). In the test mode, a test tone is provided to the mixer inputs. The test tone is divided down further and provided to clock the frequency synthesizer, the ADCs and the DSP. This configuration locks together the mixers, frequency synthesizer, ADCs and DSP ratiometrically in frequency during the test mode while image correction information is being determined. When the receiver switches to a normal operating mode, the frequency synthesizer, ADCs and DSP are clocked by a main clock signal instead of the divided down test tone, and the test tone is removed from the mixers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.