Sliced crossbar architecture with no inter-slice communication
US7584320B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2007 |
| Grant date | Sep 1, 2009 |
| Priority date | — |
| Expiry date | Sep 25, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/1523
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory crossbar adapted to transmit a memory transaction to a network resource. The memory crossbar includes a plurality of input ports. Each of the plurality of input ports includes a TAGS generator and a queue adapted to receive a first portion of a first memory transaction and a first portion of a second memory transaction. Each of the plurality of inputs ports also includes an arbiter coupled to the queue and adapted to independently select either the first portion of the first memory transaction or the first portion of the second memory transaction based on a priority associated with the first portion of the first memory transaction and the first portion of the second memory transaction and a multiplexer coupled to the arbiter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.