Memory address and datapath multiplexing
US7584321B1 · kind B1 · utility
4Cited by
9References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2003 |
| Grant date | Sep 1, 2009 |
| Priority date | — |
| Expiry date | May 29, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/18
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Circuits, methods, and apparatus for multiplexing addresses and data at a memory interface such that multiple data widths are provided without the need to change a motherboard or other printed circuit board design. A specific embodiment of the present invention achieves this using a single integrated circuit design where the datapath width is selected using a bonding option, fuse, data input, or other selection mechanism. The specific embodiment supports both 64 and 128-bit datapaths, though other numbers of datapaths, and other datapath widths are supported by other embodiments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.