Method, apparatus, and a system for efficient context switch
US7584328B2 · kind B2 · utility
5Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2005 |
| Grant date | Sep 1, 2009 |
| Priority date | — |
| Expiry date | May 26, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A discussion of a local memory with at least a command block section and a cache section that facilitates an efficient interrupt processing. The command-block section is allocated on a per interrupt basis and contains pointers to cache-lines. When an interrupt is recognized an interrupt, the proposal uses the pointers in the command-block to prefetch the corresponding cache-lines from the cache section of the local memory, which it loads into its local cache buffer. Thus, when the CPU recognizes an interrupt, the information for the context-switch is already available in cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.