Method and apparatus for debugging embedded systems having read only memory
US7584456B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2005 |
| Grant date | Sep 1, 2009 |
| Priority date | — |
| Expiry date | Aug 17, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable logic device (PLD) is provided. The PLD includes a microprocessing unit (MPU) and a memory region functioning in a read only state. A Joint Test Action Group (JTAG) debug module in communication with the memory region is included in the PLD. The JTAG debug module is able to detect a breakpoint causing an interruption of a processing sequence executed by the MPU. Write control circuitry capable of issuing a signal enabling the memory region to transition from the read only state disallowing writes to a second state accepting write data from the MPU is included in the JTAG debug circuitry. In one embodiment, the write control circuitry issues the signal in response to a breakpoint induced either through hardware or software. A method of debugging a PLD is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.