Alignment sensing method for semiconductor device
US7586202B2 · kind B2 · utility
1Cited by
5References
2Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 13, 2002 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | Jan 20, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Strip-shaped alignment marks 14 are juxtaposed with each other in a silicon oxide film 12 formed on a silicon wafer 10. Each alignment mark 14 comprises a plurality of grooves 16 formed side by side in the silicon oxide film 12. An amorphous silicon film 18 is buried in the grooves 16. Thus, the alignment marks 14 are formed in a thus-formed line-and-space pattern. Accordingly, waveforms of detected signals having high contrast and little deformation can be obtained, and alignment of wafers with high accuracy can be realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.