Dynamic delay or advance adjustment of oscillating signal phase
US7586344B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2007 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | Jan 4, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/406
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the invention can be a clock-generating circuit having one or more clock-processing circuits, each outputting a clock signal having an adjustable phase. Each clock-processing circuit comprises a divider and a divisor control circuit. Each divider divides an input clock signal by a respective divisor value and outputs a corresponding output clock signal whose period is determined by the divisor value and the period of the input clock signal. Each divider receives the respective divisor value from the corresponding divisor control circuit, wherein the divisor value is selected in order to achieve a desired frequency and phase for the corresponding output clock signal. Temporarily changing a divisor value can advance or delay the phase of the corresponding output clock signal without having to reset the divider.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.