Programmable packet parsing processor
US7586851B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2004 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | Dec 3, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention provides a packet processing device and method. A parsing processor provides instruction-driven content inspection of network packets at 10-Gbps and above with a parsing engine that executes parsing instructions. A flow state unit maintains statefulness of packet flows to allow content inspection across several related network packets. A state-graph unit traces state-graph nodes to keyword indications and/or parsing instructions. The parsing instructions can be derived from a high-level application to emulate user-friendly parsing logic. The parsing processor sends parsed packets to a network processor unit for further processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.