Systems and methods for offset cancellation in integrated transceivers
US7586983B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2006 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | Mar 8, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03057
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In high speed receiver circuitry (e.g., on a programmable logic device (PLD) or the like), decision feedback equalization (DFE) circuitry is used to at least partly cancel unwanted offset (e.g., from other elements of the receiver). The data input to the receiver is tristated; and then each DFE tap coefficient is varied in turn to find coefficient values that are associated with transitions between oscillation and non-oscillation of the receiver output signal. The coefficient values found in this way are used to select trial values. If the output signal of the receiver does not oscillate when these trial values are used, the process is repeated starting from these (or subsequent) trial values until a final set of trial values does allow oscillation of the receiver output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.