High speed data link with transmitter equalization and receiver equalization
US7586987B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2003 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | May 6, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/144
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A high speed data link includes transmitter equalization and (passive) receiver equalization to compensate for frequency distortion of the data link. In one embodiment, the transmitter equalization is performed with a de-emphasis circuit. The transmitter de-emphasis circuit pre-distorts an input signal to compensate for at least some of the frequency distortion in the data caused by the transmission line. The (passive) receive equalization circuit further compensates for the frequency distortion at the output of the transmission line to flatten the amplitude response of the output signal, and thereby reduce inter-symbol interference, improve media reach and improve the bit error rate (BER).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.