Digital-data receiver synchronization method and apparatus
US7587011B2 · kind B2 · utility
3Cited by
23References
16Claims
0Family size
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Key dates
| Filing date | Apr 26, 2005 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | Mar 5, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0685
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Digital data receiver synchronization is provided with composite phase-frequency detectors, mutually cross-connected comparison feedback or both to provide robust reception of digital data signals. A single master clock can be used to provide frequency signals. Advantages can include fast lock-up time in moderately to severely noisy conditions, greater tolerance to noise and jitter when locked, and improved tolerance to clock asymmetries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.