Power control with standby, wait, idle, and wakeup signals
US7587525B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2006 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | Nov 11, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for conserving power in a memory information transfer system. The system may include a direct memory access (DMA) controller coupled to a memory storage device and a peripheral device. The DMA controller transfers information from the memory storage device to a buffer in the peripheral device. The DMA controller may also transfer information from the buffer in the peripheral device to the memory storage device. When the peripheral device buffer does not have to be filled or emptied by the DMA controller, the DMA controller enters a standby mode. When the peripheral device buffer is full or empty, the DMA controller exits standby mode, empties or fills the peripheral device buffer, and reenters standby mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.