Data sharing apparatus and processor for sharing data between processors of different endianness
US7587557B2 · kind B2 · utility
7Cited by
11References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2004 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | Mar 19, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4013
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The data sharing apparatus in the present invention includes a first processor and a second processor, each of a different endianness, that are both connected to the memory via the data bus, in a byte order based on the endianness of the first processor. It also includes an address conversion unit which converts at least one lower bit of an address to indicate a reversed position of data in the data bus, and outputs the converted address to the memory, in the case where the second processor performs a memory access on the shared memory for data with a smaller width than the data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.