Pipelined access by FFT and filter units in co-processor and system bus slave to memory blocks via switch coupling based on control register content
US7587577B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2006 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | Dec 19, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system architecture including a co-processor and a memory switch resource is disclosed. The memory switch includes multiple memory blocks and switch circuitry for selectably coupling processing units of the co-processor, and also a bus slave circuit coupled to a system bus of the system, to selected ones of the memory blocks. The memory switch may be constructed as an array of multiplexers, controlled by control logic of the memory switch in response to the contents of a control register. The various processing units of the co-processor are each able to directly access one of the memory blocks, as controlled by the switch circuitry. Following processing of a block of data by one of the processing units, the memory switch associates the memory blocks with other functional units, thus moving data from one functional unit to another without requiring reading and rewriting of the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.