System and method of integrated circuit testing
US7587643B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 25, 2005 |
| Grant date | Sep 8, 2009 |
| Priority date | — |
| Expiry date | Jan 1, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318558
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit may include a packet decoder to receive serial data and to decode JTAG signals from the packets received. A JTAG processor may test the electrical circuitry dependent on the JTAG signals decoded. In a further embodiment, a test system may include a library of selectable JTAG routines. An encoder may encode a signal with serial data representative of sequential JTAG signals for at least one of the selectable JTAG routines. In a method of testing, the integrated circuit may receive the serial data signal at a predetermined terminal. A portion of the serial data may be examined to determine the presence of a predefined signature key. JTAG data may then be parsed from the serial data and tests performed based on the parsed JTAG data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.