Method of fabricating vertical thin film transistor
US7588971B2 · kind B2 · utility
24Cited by
9References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 17, 2007 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Jan 20, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/951
Abstract
A method of fabricating a vertical thin film transistor (vertical TFT) is disclosed, wherein a shadow mask is used to fabricate the TFT device in vertical structure. First, a metal layer is formed, which serves as ribs and a gate layer. Next, a shadow mask is disposed on the gate layer. Afterwards, the shadow mask is used as a mask to form a source layer, an organic semiconductor layer and a drain layer. Thus, the process is simplified. Since no photolithography process is required, and therefore damage of the organic semiconductor layer is avoided and a vertical TFT with desired electrical characteristics may be obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.