Field effect transistor and manufacturing method thereof
US7589381B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2006 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Sep 13, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A field effect transistor includes a first semiconductor region forming a channel region, a gate electrode insulatively disposed above the first semiconductor region, source and drain electrodes formed to sandwich the first semiconductor region in a channel lengthwise direction, and second semiconductor regions formed between the first semiconductor region and the source and drain electrodes and having impurity concentration higher than the first semiconductor region. The thickness of the second semiconductor region in the channel lengthwise direction is set to a value equal to or less than depletion layer width determined by the impurity concentration so that the second semiconductor region is depleted in a no-voltage application state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.