Shielded through-via
US7589390B2 · kind B2 · utility
37Cited by
14References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 10, 2006 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Jan 30, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09809
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A shielded through-via that reduces the effect of parasitic capacitance between the through-via and surrounding wafer while providing high isolation from neighboring signals. A shield electrode is formed in the insulating region and spaced apart from the through-via. A coupling element couples at least the time-varying portion of the signal carried on the through-via to the shield electrode. This reduces the effect of any parasitic capacitance between the through-via and the shield electrode, hence the surrounding wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.