Method of manufacturing a semiconductor device having damascene structures with air gaps
US7589425B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2005 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Feb 16, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises providing a substantially planar layer having a first metal layer, depositing a via level dielectric layer, patterning the via level dielectric layer, at least partly etching the via level dielectric layer, depositing a disposable layer on the at least partly etched via level dielectric layer, patterning the disposable layer, depositing a second metal layer, planarizing second metal layer, depositing permeable dielectric layer after planarizing the second metal layer, and removing the disposable layer through the permeable dielectric layer to form air gaps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.