Integrated circuit with redundancy
US7589552B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2007 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Oct 23, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0075
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Integrated circuits such as programmable logic devices are provided that have circuit blocks such as memory blocks. The integrated circuits may be tested to determine whether the circuit blocks contain defects. If defective circuitry is identified, switching circuitry in the circuit blocks can be configured to switch redundant circuitry into use. Repairs may be made by loading repair data into fuses on the integrated circuit. Each circuit block may have an associated control circuit with a unique address. A master block repair controller may be used to route repair data to each control circuit over a shared bus using the unique addresses of the control circuits. Each control circuit may have register circuitry into which addresses and repair data are loaded. Testing circuitry may be used to supply test signals. Multiplexing circuitry can selectively route either the test signals or repair data to the control circuits over the shared bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.