Comparator with self-biased reference voltage for an oscillator
US7589569B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2007 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Jan 15, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/354
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A comparator with a fixed reference voltage (self bias) for an oscillator is disclosed. The comparator includes: a depletion MOS network to form a source current, wherein the gate and the source has a connection; and an enhanced MOS transistor, wherein the drain or the source connects with the depletion MOS transistor in series. The gate of the enhanced MOS transistor receives an input voltage when the input voltage is lower than the reference voltage, and the comparator outputs a high level voltage, or the enhanced MOS transistor outputs a low level voltage if the input voltage is higher then the reference voltage. Moreover, the oscillator's comparator has a reference voltage that is independent from temperature and supply voltage source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.