Output architecture for LCD panel column driver
US7589653B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2008 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Jan 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/662
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital to analog converter (DAC) circuit operates over an upper range and a lower range. An upper voltage node is designated AVDD; a middle voltage node is designated HVDD; and a lower voltage node designated ground. An upper DAC stage has at least one NMOS transistor that produces an output to an upper range output node when the output is in the upper range. A lower DAC stage has at least one PMOS transistor that produces an output to a lower range output node when the output is in the lower range. A body bias control circuit couples the body of the upper NMOS transistor to a voltage source equal to HVDD−Vbe and connects the body of the lower PMOS transistor to voltage source equal to HVDD+Vbe.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.