Nonvolatile semiconductor memory having a plurality of interconnect layers
US7590004B2 · kind B2 · utility
15Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2006 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Mar 22, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory includes a memory cell array including horizontally aligned memory cell columns, each including vertically arranged memory cell transistors and select transistors selecting the memory cell transistors; first cell well lines connecting well regions in which the memory cell columns are formed; second cell well lines arranged in an interconnect layer above the first cell well lines and connecting the first cell well lines to one another electrically; and a cell source line connecting source terminals of the select transistors in each memory cell column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.