Systems and methods for clean DQS signal generation in source-synchronous DDR2 interface design
US7590025B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2007 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Mar 4, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for generating a signal to synchronize DQ data transfer in memory interface design is presented. The presented method includes receiving a strobe signal having a preamble period before and post-amble period after data transfer burst synchronization signal edge transitions, determining a timing location of the strobe signal preamble period, determining a timing location of the strobe signal post-amble period, and generating a clean strobe signal that tracks the data transfer burst synchronization edge transitions of the strobe signal after the strobe signal preamble begins and before the strobe signal post-amble ends based on the respective determined timing locations of the strobe signal preamble and post-amble periods. In this manner, DQ data transfer may be synchronized according to the burst synchronization signal edge transitions and errors caused by strobe signal level jitter during the preamble and post-amble periods are reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.