Method and apparatus for soft-error immune and self-correcting latches
US7590907B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2008 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Jul 6, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/267
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A scanned value is stored by loading the value into at least three latch stages, generating an output value based on a majority of the latch stage outputs, and feeding the output value back to the inputs of the latch stages to reload the latch stages with the latch circuit output value. Refreshing of the latch stages in this manner repairs any upset latch stage and restores the latch circuit to its original scanned state. The latch circuit may be repeatedly refreshed, preferably on a periodic basis, to prevent failures arising from multiple upsets. The feedback path may include a front-end multiplexer which receives the scan-in line and the output of the majority gate. Control logic selects the output value from the majority gate to pass to the latch stages during the refresh phase. The latch stages may be arranged in a master-slave configuration with a check stage at the slave level. The method is particularly suited for self-correcting scan latches of a microprocessor control system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.