Reduced complexity error correction encoding techniques

US7590920B2 · kind B2 · utility

Assignee

• Hitachi Global Storage Technologies Netherlands B.V. · NL

Inventors

• Shaohua Yang · Santa Clara, US
• Mario Blaum · San Jose, US
• Richard Leo Galbraith · Rochester, US
• Ksenija Lakovic · San Jose, US
• Yuan Xing Lee · San Jose, US
• Travis Roger Oenning · Rochester, US
• Jongseung Park · Allentown, US
• Hideki Sawaguchi · Kodaira, JP

Key dates

• Filing date: Aug 5, 2005
• Grant date: Sep 15, 2009
• Expiry date: Mar 16, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03M13/152
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

An error correction encoder inserts redundant parity information into a data stream to improve system reliability. The encoder can generate the redundant parity information using a composite code. Dummy bits are inserted into the data stream in locations reserved for parity information generated by subsequent encoding. The error correction code can have a uniform or a non-uniform span. The span corresponds to consecutive channel bits that are within a single block of a smaller parity code that is used to form a composite code. The span lengths can be variant across the whole codeword by inserting dummy bits in less than all of the spans.