Compact chip package macromodels for chip-package simulation
US7590952B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2006 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Aug 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer implemented method, data processing system, and computer usable program code are provided for reducing a chip package model. Responsive to receiving the chip package model, an inductance and a resistance of the chip package model is measured. The inductance and the resistance are measured using only a set of external nodes of the chip package model. A reduced node resistor model and a reduced node inductor model are created using the inductance and the resistance of the chip package model. A combined reduced node resistor-inductor chip package model is formed by combining the reduced node resistor model and reduced node inductor model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.