Method and system for automatic generation of processor datapaths using instruction set architecture implementing means
US7590964B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2005 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Jan 25, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on the ISA. Such operations, for example, may represent a configurable processor ISA. The operations may also include one or more extension operations defined by one or more designers. Thus, a description of the behaviors of the various standard and/or extension operations that compose the ISA of an instance of a standard or configurable processor is used to automatically generate a set of shared processor datapaths that implement the behavior of those operations. In addition, certain aspects may take one or more operations as well as one or more input semantics and either re-implement the input semantics automatically, or combine the input semantics with each other or with one or more other operations to automatically generate a new set of shared processor datapaths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.