System and method for virtualizing processor and interrupt priorities
US7590982B1 · kind B1 · utility
31Cited by
3References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 26, 2004 |
| Grant date | Sep 15, 2009 |
| Priority date | — |
| Expiry date | Oct 12, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Dispatching of interrupts to a processor is conditionally suppressed, that is, only if an old priority value and a new priority value are either both less than or both greater than a maximum pending priority value. This conditional avoidance of dispatching is preferably implemented by a virtual priority module within a binary translator in a virtualized computer system and relates to interrupts directed to a virtualized processor by a virtualized local APIC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.