Fuse region and method of fabricating the same
US7592206B2 · kind B2 · utility
4Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2006 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Mar 2, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment a fuse region includes an insulating layer disposed on a substrate, a fuse disposed on the insulating layer and including a fuse barrier pattern and a fuse conductive pattern, which are stacked, and a supporting plug disposed beneath the fuse, and penetrating the insulating layer and the fuse barrier pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.