Semiconductor device having well with peak impurity concentrations and method for fabricating the same
US7592241B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 22, 2004 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Jul 30, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0191
Abstract
The semiconductor device comprises a well 58 formed in a semiconductor substrate 10 and having a channel region; a gate electrode 34n formed over the channel region with an insulating film 32 interposed therebetween; source/drain regions 60 formed in the well 58 on both sides of the gate electrode 34n, sandwiching the channel region; and a pocket region 40 formed between the source/drain region and the channel region. The well 58 has a first peak of an impurity concentration at a depth deeper than the pocket region 40 and shallower than the bottom of the source/drain regions 60, and a second peak of the impurity concentration at a depth near the bottom of the source/drain regions 60.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.