Memory word lines with interlaced metal layers

US7592649B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Shine C. Chung · San Jose, US
• Cheng-Hsien Hung · Allen, US

Key dates

• Filing date: Apr 10, 2008
• Grant date: Sep 22, 2009
• Expiry date: Apr 10, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/488

Abstract

A memory device with improved word line structure is disclosed. The memory device includes a plurality of polysilicon strips substantially parallel to each other on the substrate, the plurality of polysilicon strips arranged in two interleaved groups of a first group and a second group. The memory device further includes a first layer of conductive strips forming a plurality of bit lines and a second layer of meal strips, the second layer of conductive strips overlying the polysilicon strips and coupled to the first group of polysilicon strips. In addition, the memory device includes a third layer of conductive strips forming one or more power line, and a fourth layer of metal strips, the fourth layer of conductive strips overlying the second layer of conductive strips and coupled to the second group of polysilicon strips to form a new word line structure having a low resistance.