Patent · US Active

Systems and methods involving field programmable gate arrays

US7592833B1 · kind B1 · utility

2Cited by
4References
19Claims
0Family size

Assignee

Inventor

Key dates

Filing dateMay 15, 2008
Grant dateSep 22, 2009
Priority date—
Expiry dateMay 15, 2028

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F30/34
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A method for programming logic in a field programmable gate array (FPGA) comprising, receiving a logic process including a logic node, and associating the node with a logic descriptor, and saving the logic descriptor in a memory of the FPGA. The logic descriptor including: a unique identifier of the node, an enabling indicator operative to indicate if the node is enabled, a function indicator operative to define a logic function performed by the node, an input number indicator operative to define a number of inputs of the node, an output indicator operative to indicate a logic state of an output of the node, and an input indicator operative to indicate a unique identifier of an input of the node.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.