Delay management circuit for reading out large S/H arrays
US7593050B2 · kind B2 · utility
1Cited by
8References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2006 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Oct 8, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/7795
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An image sensor includes a plurality of pixels for capturing an image; a sample and hold circuit array having a plurality of units for receiving signals from the plurality of pixels representing the captured image; a decoder for selecting each of the units of the sample and hold circuit array for output; and a delay circuit that includes an adjustable time delay to the decoder for compensating for time delays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.