Memory array with readout isolation
US7593256B2 · kind B2 · utility
6Cited by
25References
28Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 28, 2007 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Aug 13, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for differentially measuring the bit state of a particular element in an array of passive nonlinear elements against the output of a reference generator. The reference generator may be, for example, a dummy row circuit, a dummy column circuit, or both a dummy row circuit and a dummy column circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.