Method for performing high resolution phase alignment of multiple clocks using low resolution converters
US7593495B2 · kind B2 · utility
0Cited by
2References
11Claims
0Family size
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Key dates
| Filing date | Mar 30, 2006 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Sep 16, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The offset between a reference clock output signal and a target clock output signal are measured during a predetermined period. Based on the measurement, an offset signal is generated. The offset signal is integrated into an average offset signal value, wherein the period of integration is the predetermined phase measurement time. The target clock is adjusted based on the average offset signal value so that the offset signal magnitude value approaches a predetermined limit. The process is iterated until the clocks are aligned within a predetermined tolerance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.