Method and apparatus for adjustment of synchronous clock signals
US7593497B2 · kind B2 · utility
6Cited by
19References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 31, 2005 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Sep 4, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A synchronous clock signal can be adjusted relative to a data signal by decreasing a delay in the synchronous clock signal if a transition of a data signal occurs before a pulse of an offset clock signal which is delayed by one half cycle relative to the synchronous clock signal. The synchronous clock signal can be delayed if the transition of the data signal occurs after the pulse of the offset synchronous clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.