Receiver assembly and method for multi-gigabit wireless systems
US7593704B2 · kind B2 · utility
91Cited by
7References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2006 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Jul 21, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B7/0808
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The present invention describes a receiver assembly for receiving an analog signal and converting the analog signal to a digital signal. The receiver assembly is, preferably, capable of receiving a signal operating at approximately 60 GHz. The receiver assembly includes a filter, a down converter, a demodulator, a latch, a FIFO, and a logic circuit. A method of converting the 60 GHz analog signal to a digital signal is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.