Method and apparatus for single instruction multiple data caching
US7594069B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2004 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Jun 24, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for single instruction multiple data caching includes a memory access request generator operative to receive a primary access request. The method and apparatus further includes a cache controller coupled to the memory access request generator, wherein the cache controller is operative to execute a memory request. The method and apparatus further includes a memory interface coupled to the cache controller, the memory interface operative to retrieve a plurality of requested data. The method and apparatus further includes a request processor coupled to the cache controller, the memory interface and the memory access request generator. The request processor is operative to receive a plurality of requested data and thereupon generate a plurality of parallel data outputs therefrom.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.