Processes and devices for compression and decompression of executable code by a microprocessor with RISC architecture and related system
US7594098B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 2006 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Sep 25, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/4434
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An embodiment of the invention relates to a process for compression of executable code by a microprocessor, comprising decomposing the executable code into words; dividing the executable code into instruction lines; compressing each word of each line in the form of a compressed word of variable length, the compressed words of a line being combined into a line of compressed words; and constituting an addressing table localizing each of the lines of compressed words in a block of lines compressed words and comprising one input per group of lines of compressed words, each input (j) specifying the position of a first line of compressed words in the block, and the respective lengths of the lines of compressed words of group, except for a last line of compressed words of the group, whereof the length is determined by means of the position of a first line of compressed words of a following group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.