Processor executing SIMD instructions
US7594099B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2007 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Aug 31, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/38
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.