Handling fatal computer hardware errors
US7594144B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2006 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Oct 9, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0745
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are disclosed for handling fatal computer hardware errors on a computer that include halting data processing operations of the computer upon occurrence of a fatal hardware error; signaling by a source chip of a chipset to the programmable logic device the occurrence of a fatal hardware error; signaling by the programmable logic device to an embedded system microcontroller the occurrence of a fatal hardware error; reading by the embedded system microcontroller through at least one sideband bus from registers in chips of the chipset information regarding the cause of the fatal hardware error; and storing by the embedded system microcontroller the information in non-volatile random access memory of the embedded system microcontroller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.