Improving performance of a processor having a defective cache
US7594145B2 · kind B2 · utility
2Cited by
5References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 2006 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Jun 3, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method for improving performance of a processor having a defective cache includes accessing first object code and generating second object code from the first object code. The generation of the second object code takes into account one or more locations of one or more defects in a cache on a processor such that one or more instructions in the second object code are written only to nondefective locations in the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.