Enhanced method of optimizing multiplex structures and multiplex control structures in RTL code
US7594201B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2006 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Aug 9, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of method of optimizing register transfer level code for an integrated circuit design comprising steps of receiving as input a first register transfer level code for the integrated circuit design and receiving as input criteria defining a critical multiplex structure. The first register transfer level code is analyzed to identify multiplex structures in the first register transfer level code. Each of the multiplex structures identified in the first register transfer level code is compared to the criteria defining a critical multiplex structure. Each of the multiplex structures identified in the first register transfer level code that satisfy the criteria defining a critical multiplex structure is entered in a list of critical multiplex structures. The list of critical multiplex structures is generated as output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.