Straight-line post-increment optimization for memory access instructions
US7594223B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2005 |
| Grant date | Sep 22, 2009 |
| Priority date | — |
| Expiry date | Dec 21, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compiler configured for optimizing non-loop memory access instructions of a computer program to form architected memory instructions conforming to a base register auto-incrementing addressing mode. The compiler includes code for obtaining an intermediate stream of code containing pseudo-memory instructions from the non-loop memory access instructions. The intermediate stream of code includes at least one place holder instruction preserving a value associated with a base of a first non-loop memory access instruction even after the first non-loop memory instruction is converted to one of the pseudo-memory instructions. The compiler includes code for converting the intermediate stream of code using the intermediate stream of code and the at least one place holder instruction to obtain the architected memory instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.