Method for manufacturing compound semiconductor substrate with pn junction
US7595259B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2005 |
| Grant date | Sep 29, 2009 |
| Priority date | — |
| Expiry date | Oct 10, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D8/045
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A compound semiconductor substrate manufacturing method suitable for manufacturing a compound semiconductor element having high electrical characteristics. The compound semiconductor substrate manufacturing method is a method for manufacturing a compound semiconductor substrate having pn junction, including an epitaxial growing process, a selective growing process and other discretionary processes after the epitaxial growing process. The highest temperatures in the selective growing process and other discretionary processes after the epitaxial growing process are lower than that in the epitaxial growing process prior to the selective growing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.