Semiconductor integrated circuit devices having upper pattern aligned with lower pattern molded by semiconductor substrate and methods of forming the same
US7595529B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2008 |
| Grant date | Sep 29, 2009 |
| Priority date | — |
| Expiry date | Jul 18, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
Abstract
Provided are semiconductor integrated circuit (IC) devices having an upper pattern aligned with a lower pattern molded by a semiconductor substrate and methods of forming the same. In the semiconductor IC devices, the lower pattern contacts the upper pattern using an active region and/or an isolation layer. The methods include preparing a semiconductor substrate having an active region. A lower pattern is formed on the active region. The lower pattern is surrounded by the active region and protrudes from a top surface of the active region. An upper pattern is disposed on the lower pattern. The upper pattern contacts the lower pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.