Layers in substrate wafers

US7595534B2 · kind B2 · utility

Assignee

• IHP-GmbH - Innovations for High Performance Microelectronics/Institut fur Innovative Mikroelektronik · DE

Inventors

• Bernd Heinemann · Frankfurt, DE
• Karl-Ernst Ehwald · Frankfurt, DE
• Dieter Knoll · Frankfurt (Oder), DE
• Bernd Tillack · Frankfurt (Oder), DE
• Dirk Wolansky · Frankfurt, DE
• Peter Schley · Essen, DE

Key dates

• Filing date: Dec 6, 2001
• Grant date: Sep 29, 2009
• Expiry date: Dec 6, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The invention relates to layers in substrate wafers. The aim of the invention is to provide layers in substrate wafers with which the drawbacks of conventional assemblies are overcome in order to achieve, on the one hand, an adequate resistance to latch-up in highly scaled, digital CMOS circuits with comparatively low costs and, on the other hand, to ensure low substrate losses/couplings for analog high-frequency circuits and, in addition, to influence the component behavior in a non-destructive manner. To these ends, the invention provides that in a highly resistive p-Si substrate (2) with one or more buried high-carbon Si layers (3) under an epitaxial layer and with the Si cap layer (4), an implantation dose, which is greater in comparison to conventional substrate wafers, is used for retrograde trough profiles by suppressing the dopant diffusion as well as the generation of defects when remedying implant defects, thereby achieving a reduction of the trough resistance, and finally, an increase in the resistance to latch-up.