Plasma display panel
US7595589B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2005 |
| Grant date | Sep 29, 2009 |
| Priority date | — |
| Expiry date | Oct 9, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2211/326
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A plasma display that includes a lower substrate and an upper substrate arranged opposite to each other and separated by a constant distance, with a discharge space being arranged between the substrates, a plurality of partitions arranged between the lower substrate and the upper substrate that partition the discharge space into a plurality of discharge cells, a plurality of address electrodes arranged on an upper surface of the lower substrate, a first dielectric layer arranged on the upper surface of the lower substrate and covering the address electrodes, a plurality of first sustain electrodes arranged on a lower surface of the upper substrate and having the shape of a closed loop corresponding to each discharge cell, a plurality of second sustain electrodes arranged between the upper substrate and the lower substrate and having a shape of a closed loop corresponding to closed loops in the first sustain electrodes, and a phosphor layer arranged on the upper surface of the first dielectric layer and on sidewalls of the partitions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.